Input Buffer Control Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The buffer input control registers include:

  • Internal pull-up enable
  • Internal pull-down enable
  • Schmitt trigger enable

There is also a voltage mode status bit for each MIO bank. This does not affect the functionality of the I/O buffer.

Internal Pull-up and Pull-down Enables

Each I/O buffer has a weak pull-up and pull-down option. If both the pull-up and pull-down bits are set = 1, the I/O buffer weakly holds the output to its last driven state.

Schmitt Trigger Input Enable

The I/O buffer includes a Schmitt trigger hysteresis option.

Voltage Mode Status

The nominal I/O voltage is detected by analog circuitry and reported in the VMode registers; this are read-only registers.

Table 1. MIO Input Buffer Control Registers
Feature PMC_IOP_SLCR Registers LPD_IOP_SLCR Registers Description
PMC MIO Bank 0 PMC MIO Bank 1 PS LPD MIO Bank
Pins 0 to 25 Pins 26 to 51 Pins 0 to 25
Weak pull-up MIO_Bank0_PU_En MIO_Bank1_PU_En MIO_Bank2_PU_En

0: Disable
1: Enable

Weak pull-down MIO_Bank0_PD_En MIO_Bank1_PD_En MIO_Bank2_PD_En
Schmitt trigger MIO_Bank0_Schmitt_En MIO_Bank1_Schmitt_En MIO_Bank2_Schmitt_En
Voltage mode MIO_Bank0_VMode MIO_Bank1_VMode MIO_Bank2_VMode

Read-only:
0: 2.5/3.3V
1: 1.8V