Integrated Debug Block Diagram

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The following figure shows the debug host interfaces that are connected to the DPC.

There are four debug host interfaces. The hosts establish a packet protocol with the DPC. To create the response packet, the DPC writes to system resources via the DPC interconnect switch.

Note: The interconnect interfaces are shown in the Interconnect Switch Diagrams section. The TPIU I/O connections are shown in the Data Flow Diagrams section.
Figure 1. Integrated Debug System Architecture Block Diagram