Integrated Silicon

Versal ACAP Technical Reference Manual (AM011)

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1.5 English

Most devices include a single die with a single PMC, a processing system, an array of programmable logic, and various integrated hardware logic. A layout with a PMC, an array of programmable logic and integrated hardware is referred to as a super logic region (SLR). The primary SLR includes a reduced-functionality PMC and a processing system.

Some devices include multiple SLRs with scalable PL layouts, integrated hardware, and I/O structures. There are monolithic designs with one or more SLRs. There are multi-die SSI technology devices with interposer layers.

Devices are listed in the Versal Architecture and Product Data Sheet: Overview (DS950).

This chapter includes conceptual content with multiple SLRs. The physical layouts are numerous, and include devices with scalable PL fabric CFRAME arrays, optional integrated hardware accelerators and peripherals, and many different layouts that can be mirrored and modularized.

A few examples are shown to provide a conceptual picture of the integrated silicon possibilities.