Interconnect Clock Frequency Requirements

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The interconnect includes low-speed APB, top switch AXI, and the NPI.

  • Low-speed bus clock for APB in PMC and PS programming interfaces
  • Top-switch clocks for AXI interconnect
  • NPI clock for memory mapped registers in NoC, DDRMC, AI Engine, and other integrated hardware

Low-speed Bus Clocks

The low-speed bus (LSBUS) clocks drive the APB programming interfaces.

Top Switch Interconnect Switch Clocks

The LPD_TOPSW_CLK clock frequency must always be set higher than the LPD_LSBUS_CLK clock frequency.

The FPD_TOPSW_CLK clock frequency must always be set higher than the FPD_LSBUS_CLK clock frequency. This clock is used on the FPD main switch and the auxiliary FPD switch for AXI port interfaces.

NPI Reference Clock

The NPI_REF_CLK is used to clock several blocks.

  • NPI programming interfaces to the NPI register modules
  • GTs in the PL
Because the NPI_REF_CLK is used by the GTs in the PL, its frequency must be set accurately to 300 MHz.
Note: The NPI_REF_CLK specification is in the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957).