JTAG Boot Mode

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English
The JTAG interface is a multipurpose interface used for both boot and debug functions (PMC TAP JTAG operations, Arm® DAP debug, and interfaces to the debug packet controller for ChipScope™ solution debug). Due to this flexibility, the JTAG boot mode is popular for initial design bring-up and is a recommended interface for all applications. The JTAG boot mode uses only dedicated I/O. During boot, the BootROM sets configuration registers that apply to each boot mode. For JTAG boot mode, the BootROM sets the registers to the initial values shown in the following table.
Table 1. BootROM Initialization for JTAG
Register Name Base Address Register Value Description
Dst_Ctrl2 0xF11D_0824 0x081B_FFF8 DST DMA setup
RST_SBI 0xF126_0324 0x0000_0000 SBI RST not asserted
SBI_MODE 0xF122_0000 0x0000_0002 Device configuration mode, JTAG pass through SBI (PDI loading)
SBI_CTRL 0xF122_0004 0x0000_0025 JTAG mode data transfer, SBI enabled
PMCPLL_CTRL 0xF126_0040 0x0002_4800 PMC PLL (PPLL) setup uses reset defaults ( REF_CLK multiplied by 72 (FBDIV) and divided by 4 (CLKOUTDIV))

See Test and Debug for information on JTAG instructions and JTAG chain.

Table 2. JTAG Boot Mode Interface
Pin Name Pin Type Direction Description
TDI Dedicated Input Test data input
TDO Dedicated Output Test data output
TMS Dedicated Input Test mode select
TCK Dedicated Input Test clock