JTAG System Perspective

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The JTAG interface provides access to the Arm DAP and JTAG TAP controllers. The interface is compatible with the IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std 1149.1) and includes all the mandatory elements defined by the standard. These elements include the TAP, TAP controller, instruction register, instruction decoder, boundary register, and bypass register. The controller also support a 32-bit device identification register and a JTAG configuration register that adds additional debug capability.

The primary debug access port is the JTAG interface. The JTAG chain order in the AMD Versalâ„¢ adaptive SoC is fixed with the DAP controller followed by the TAP controller as shown in the following figure.

Figure 1. JTAG Interface Chain
Note: There are additional TAP controllers in stacked silicon interconnect technology devices. See the SSI Multiple Super Logic Regions section.