JTAG TAP Instructions

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-12-16
Revision
1.5 English

The TAP instructions supported by the Versal ACAP are listed in the following table.

Table 1. JTAG TAP Instructions
Instruction Name Binary Code [5:0] 1 Hex Code Description
AUTH_JTAG 110101 35h Authenticated JTAG can enable the JTAG interface
BYPASS 111111 3Fh Enables BYPASS instruction
DPC 110110 36h Accesses the debug packet controller
ERROR_STATUS 111110 3Eh Accesses the error management status register
EXTEST 100110 26h Enables the boundary-scan EXTEST instruction
EXTEST_PULSE 111100 3Ch Enables the IEEE Std 1149.6 functions in the GTs for testing AC-coupled connections between GTs
EXTEST_TRAIN 111101 3Dh Enables the IEEE Std 1149.6 functions in the GTs for testing AC-coupled connections between GTs
HIGHZ_IO 001010 0Ah 3-stated user I/O pins but not GTs while enabling the bypass register
IDCODE 001001 09h ID Code; accesses the device IDCODE
EXTENDED_IDCODE 011001 19h ID code extended; used with IDCODE for device extended identification
JCONFIG 000101 05h Accesses the SBI for boot and configuration of the Versal ACAP via JTAG (JCONFIG)
JRDBK 000100 04h JTAG configuration; accesses the SBI for readback via JTAG
JSTATUS 011111 1Fh JTAG status: access to the device JTAG status register value
READ_DNA 110010 32h Accesses the Versal ACAP unique device DNA value
SAMPLE/PRELOAD 000001 01h Enables boundary-scan SAMPLE/PRELOAD instruction
SYS_RST 110111 37h Resets the Versal ACAP with PMC_SRST
USER1 000010 02h Access to the user-defined register 1
USER2 000011 03h Access to the user-defined register 2
USER3 100010 22h Access to the user-defined register 3
USER4 100011 23h Access to the user-defined register 4
USERCODE 001000 08h Access to the user designated value
  1. The SSI Technology devices JTAG TAP instruction length will vary. See the Versal ACAP device BSDL files for targeted SSI Technology device instruction length.