JTAG TAP Instructions

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The following table lists the TAP instructions. For SSI technology devices, see the figure in the SSI Multiple Super Logic Regions section.

Table 1. JTAG TAP Instructions
Instruction Binary Opcode Description

Device with
1 SLR [5:0]
(Monolithic)

Device with
2 SLRs [13:0]
(SSIT)

Device with
3 SLRs [20:0]
(SSIT)

Device with
4 SLRs [27:0]
(SSIT)
AUTH_JTAG 110101 11010111111111 110101111111111111111 1101011111111111111111111111 Selects the 32-bit SECURE_DEBUG data register to authenticate in secure mode and enable the JTAG interface.
BYPASS 111111 11111111111111 111111111111111111111 1111111111111111111111111111 Selects the 1-bit BYPASS data register.
DPC 110110 11011011101111 110110111011111011111 1101101110111110111110111111 Reserved for AMD Vivado™ /AMD Vitis™ tools.
ERROR_STATUS 111110 11111011111011 111110111110111110111 1111101111101111101111101111 Selects the ERROR_STATUS data register. The ERROR_Status data register length is:

1 SLR: 160-bit
2 SLRs: 322-bit
(SLR0 ERROR_STATUS [321:162]
SLR1 ERROR_STATUS[161:2]
Reserved ERROR_STATUS[1:0])
3 SLRs: 483-bit
(SLR0 ERROR_STATUS [482:323]
SLR1 ERROR_STATUS[322:163]
SLR2 ERROR_STATUS[162:3]
Reserved ERROR_STATUS[2:0])
4 SLRs: 644-bit
(SLR0 ERROR_STATUS [643:484]
SLR1 ERROR_STATUS[483:324]
SLR2 ERROR_STATUS[323:164]
SLR3 ERROR_STATUS [163:4]
Reserved ERROR_STATUS[3:0])
EXTEST 100110 10011010011011 100110100110100110111 1001101001101001101001101111 Selects the BOUNDARY data register for the boundary-scan EXTEST instruction.
EXTEST_PULSE 111100 11110011110011 111100111100111100111 1111001111001111001111001111 Selects the BOUNDARY data register to support the IEEE Std 1149.6 functions for testing AC-coupled connections between GTs.
EXTEST_TRAIN 111101 11110111110111 111101111101111101111 1111011111011111011111011111 Selects the BOUNDARY data register to support the IEEE Std 1149.6 functions for testing AC-coupled connections between GTs.
HIGHZ_IO 001010 00101000101011 001010001010001010111 0010100010100010100010101111 Selects the 1-bit BYPASS data register and 3-states user I/O pins except for GT I/O.
IDCODE 001001 00100100100111 001001001001001001111 0010010010010010010010011111 Selects the 32-bit DEVICE_IDENTIFICATION (IDCODE) data register for device identification.
EXTENDED_IDCODE 011001 01100101100111 011001011001011001111 0110010110010110010110011111 Selects the 32-bit EXTENDED_IDCODE data register for extended device identification.
JCONFIG 000101 00010111111111 000101111111111111111 0001011111111111111111111111 Reserved for Vivado/Vitis tools.
JRDBK 000100 00010011111111 000100111111111111111 0001001111111111111111111111 Reserved for Vivado/Vitis tools.
JSTATUS 011111 01111101111111 011111011111011111111 0111110111110111110111111111 Selects the JTAG_STATUS data register for platform management controller (PMC) overall status. The JTAG_STATUS data register length is:

1 SLR: 36-bit
2 SLRs: 74-bit
(SLR0 JTAG_STATUS[73:38]
SLR1 JTAG_STATUS[37:2]
Reserved JTAG_STATUS[1:0] bits)
3 SLRs: 111-bit
(SLR0 JTAG_STATUS[110:75]
SLR1 JTAG_STATUS[74:39]
SLR2 JTAG_STATUS[38:3]
Reserved JTAG_STATUS[2:0])
4 SLRs: 148-bit
(SLR0 JTAG_STATUS[147:112] SLR1 JTAG_STATUS[111:76] SLR2 JTAG_STATUS[75:40] SLR3 JTAG_STATUS[39:4] Reserved JTAG_STATUS[3:0])
READ_DNA 110010 11001011001011 110010110010110010111 1100101100101100101100101111 Selects the DNA data register to access the Versal device unique device DNA value. The DNA data register length is:

1 SLR: 128-bit
2 SLRs: 258-bit
(SLR0 DNA[257:130]
SLR1 DNA[129:2]
Reserved DNA[1:0])
3 SLRs: 387-bit
(SLR0 DNA[386:259]
SLR1 DNA[258:131]
SLR2 DNA[130:3]
Reserved DNA[2:0])
4 SLRs: 516-bit
(SLR0 DNA[515:388]
SLR1 DNA[387:260]
SLR2 DNA[259:132]
SLR3 DNA[131:4]
Reserved DNA[3:0])
SAMPLE/PRELOAD 000001 00000100000111 000001000001000001111 0000010000010000010000011111 Selects the BOUNDARY data register for the boundary-scan SAMPLE/PRELOAD instruction.
SYS_RST 110111 11011111011111 110111110111110111111 1101111101111101111101111111 Reserved for Vivado/Vitis tools.
USER1 000010 00001011101111 000010111011111011111 0000101110111110111110111111 Selects the USER1 user-defined data register (selected with CIPS BSCAN0).
USER2 000011 00001111101111 000011111011111011111 0000111110111110111110111111 Selects the USER2 user-defined data register (selected with CIPS BSCAN1).
USER3 100010 10001011101111 100010111011111011111 1000101110111110111110111111 Selects the USER3 user-defined data register (selected with CIPS BSCAN2).
USER4 100011 10001111101111 100011111011111011111 1000111110111110111110111111 Selects the USER4 user-defined data register (selected with CIPS BSCAN3).
USERCODE 001000 00100011101111 001000111011111011111 0010001110111110111110111111 Selects the 32-bit USERCODE user-designated data register.