LPD Block Resets

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The controller resets are summarized in the following table.

Table 1. LPD Block Resets
Block Reset Name   Register Control  
LPD I/O Peripherals    
GPIO controller LPD_GPIO_RESET   CRL CRL.RST_GPIO [RESET]  
I2C 0 controller LPD_I2C0_RESET   CRL CRL.RST_ I2C [RESET]  
I2C 1 controller LPD_I2C1_RESET   CRL CRL.RST_ I2C [RESET]  
USB 2.0 PHY Reset Control
USB 2.0 controller USB2_RESET   CRP CRP.RST_USB [PHY_RST]

This resets the PHY in the PMC power domain.
The USB controller is located in the LPD.

LPD Resets

The global LPD resets are included in the PS resets. The application software can request resets to the LPD blocks using the PSM Global Registers. The PSM firmware can control interconnect traffic to halt new transactions and allow any active traffic to finish if possible. If traffic stalls, this can be detected by the transaction timeout feature on each interconnect egress port.

RPU MPCore Resets

There are several reset controls resets within the RPU MPCore. For example, cores can individually be reset.