LPD Reference Clocks

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The LPD reference clocks are listed alphabetically in the following table.

Table 1. LPD IOP Reference Clock Registers
Description Clocks CRL Control Registers
Output Name Divider Input Options
CAN 0 controller CAN0_REF_CLK RPLL_CLK, PPLL_TO_XPD_CLK, NPLL_TO_XPD_CLK CAN0_REF_CTRL
CAN 1 controller CAN1_REF_CLK CAN1_REF_CTRL
GEM 0 controller GEM0_REF_CLK GEM0_REF_CTRL
GEM 1 controller GEM1_REF_CLK GEM1_REF_CTRL
GEM timestamp clock GEM_TSU_CLK GEM_TSU_REF_CTRL
LPD I2C 0 controller LPD_I2C0_REF_CLK I2C0_REF_CTRL
LPD I2C 1 controller LPD_I2C1_REF_CLK I2C1_REF_CTRL
SPI 0 controller SPI0_REF_CLK SPI0_REF_CTRL
SPI 1 controller SPI1_REF_CLK SPI1_REF_CTRL
UART 0 controller UART0_REF_CLK UART0_REF_CTRL
UART 1 controller UART1_REF_CLK UART1_REF_CTRL
USB 2.0 controller USB_2_REF_CLK USB_LPD_REF_CTRL
Table 2. LPD Miscellaneous Reference Clock Registers
Description Clocks Control Register
Output Name Divider Input Options
System counter (SCNTR) SCNTR_TS_CLK

RPLL_CLK
PPLL_TO_XPD_CLK
NPLL_TO_XPD_CLK

TIMESTAMP_REF_CTRL
CPM AXI interconnect CPM_TOPSW_CLK CPM_TOPSW_REF_CTRL
RPU: TCM, GIC, OCM, and Interconnect CPU_R5F_CLK RPU_OCM_XRAM_CTRL
LPD CoreSightâ„¢ components except the TSU.

Includes: ROM, GPR, CTI, funnel

DBG_LPD_CLK DBG_LPD_CTRL
CoreSight timestamp generator DBG_TS_CLK

RPLL_CLK
PPLL_TO_XPD_CLK
NPLL_TO_XPD_CLK

DBG_TSTMP_CTRL
AXI/AHB interconnect switch LPD_IOP_SW_CLK LPD_IOPSW_CTRL
LPD APB programming interfaces LPD_LSBUS_CLK LPD_LSBUS_CTRL
LPD AXI main switch LPD_TOPSW_CLK LPD_TOP_SWITCH_CTRL
PS manager processor PSM_REF_CLK   PSM_REF_CTRL
Divided-down RPLL_CLK routed to the clock controllers in the FPD power domains RPLL_TO_XPD_CLK RPLL_CLK RPLL_TO_XPD_CTRL