Low-speed Clock Control Settings

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The registers to control the clock frequency and tap delays are shown in the following table. These controls are also shown in the Clock Block Diagram. The registers are listed in the following table with bit field name and bit field number.

Table 1. Low-speed Clock Control Settings
SD_EMMC Register Field Name, Bits Setting Description
Clock Controls
CLK_CTRL

[SDClkFreqDiv_U, 7:6]
[SDClkFreqDiv_L, 15:8]

Depends on mode Clock frequency divider
[IntClkEn, 0] 1 Divider, DLL clock and TX output enable
[SDClkEn, 2] 1 Divider or DLL output enable
Clock Status
CLK_CTRL [IntClkStable, 1] 1

Read-only:
0: Not ready
1: Ready