MIO Boot Interface Pin Buffer Settings

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The I/O buffers for the MIO pins used to interface to the boot device are configured by the RCU BootROM with these attributes:

  • Default drive strength (8 mA)
  • Default slew rate (slow)
  • Default weak pull-ups (enabled)
  • Enables the Schmitt trigger
  • Disables the 3-state override
Note: The MIO pins that are not used for the boot interface are not configured and remain at their default reset settings.

If a secure lockdown occurs during boot, the BootROM sets the PMC_GLOBAL.TRISTATE_OVERRIDE register to force all I/Os into a tristate mode. This register is then reserved for use by the PLM firmware.