MIO Boot Interfaces

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The MIO pins used for each boot interface are shown as shaded cells in the tables in the MIO-at-a-Glance Tables section.

The interfaces are described in detail in Flash Memory Controllers, JTAG Controller Interface Pins, and SelectMAP Boot Mode Signals.

Note: The PLM firmware can configure additional signals to increase the functionality of a flash memory interface. This includes QSPI loopback clock (LPBK) for higher frequencies and the QSPI stacked architecture by programming the QSPI1 CS_b pin for additional flash memory.