MIO-EMIO Interface Routing Options

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The I/O interfaces for the IOP controllers and other units are routed to the PMC and LPD MIO multiplexers. Some signals can be routed to the EMIO interface to the PL. Some IOP interfaces and signals are only available on the MIO (e.g., quad SPI). Other I/O signals are only available on the EMIO interface (e.g., LPD DMA handshake control).

The routing is configured by the registers in the PMC_IOP_SLCR and LPD_IOP_SLCR register sets. The interfaces and signals that are routed through the MIO-EMIO are listed in the following table with their I/O interface routing options.

Table 1. MIO-EMIO Interface Routing Options
Interface or Signal Controller Location Access Notes
PMC MIO LPD MIO EMIO

CAN_FD0
CAN_FD1

LPD Yes Yes Yes  

GEM0
GEM1

LPD Yes Yes - RGMII
- - Yes GMII/MII, TSU, and external FIFO
Yes Yes Yes MDIO
LPD DMA LPD - - Yes Flow control
PMC_GPIO PMC Yes - - PMC GPIO Banks 0, 1 (no bank 2)
- - Yes PMC GPIO Banks 3, 4
LPD_GPIO LPD - Yes - LPD GPIO Bank 0 (no banks 1, 2)
- - Yes LPD GPIO Bank 3

LPD_I2C0
LPD_I2C1

LPD Yes Yes Yes  
PMC_I2C PMC Yes - Yes  
Octal SPI PMC Yes   -  

SD/eMMC0
SD/eMMC1

PMC Yes - Yes The clock frequency for the EMIO interface is <= 25 MHz
SelectMAP PMC Yes - -  

SPI0
SPI1

LPD Yes Yes Yes  
Quad SPI PMC Yes - -  
CoreSightâ„¢ Trace Out FPD 16-bit 16-bit 32-bit  

TTC0
TTC1
TTC2
TTC3

LPD Yes Yes Yes Clock in and wave out

UART0
UART1

LPD Yes Yes Yes MIO only includes RX, TX, CTS, and RTS
USB_2.0 LPD Yes - - ULPI
LPD_SWDT LPD Yes Yes Yes (SWDT0)
FPD_SWDT FPD ~ ~ ~ (SWDT1)