MIO Signal Tables

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The I/O interface is only available on the PMC MIO pins. The interface is not available on the LPD MIO pins or the PL EMIO interface.

The QSPI controller signals are listed in the following tables. The interface includes lower and upper controls, QSPI0 and QSPI1, respectively. The controller always drives the interface clock signal as an output.

Table 1. Quad SPI Flash Interface I/O Signals
Versal ACAP Signal Name Flash Interface Protocols
1-bit 2-bit 4-bit
I/O Name I/O Name I/O Name
QSPIx_CLK O CLK O CLK O CLK
QSPIx_CS_b O CS_b O CS_b O CS_b
QSPIx_IO[0] O MOSI I/O IO[0] I/O IO[0]
QSPIx_IO[1] I MISO I/O IO[1] I/O IO[1]
QSPIx_IO[2] O WP_b O WP_b I/O IO[2]
QSPIx_IO[3] O HOLD_b O HOLD_b I/O IO[3]
QSPI_LPBK_CLK Enable for clock frequencies >37.5 MHz; it is a no connect on the PCB.

MIO Configuration Table

The five MIO connection options are shown in Wiring Diagrams and are listed in the following table.

Note: The loopback clock signal is routed from the controller through the output buffer to the pin and returned back through the pin's input buffer to the controller for I/O delay compensation. The loopback clock signal is used by both QSPIx_CLK outputs via a clock gating circuit.
Table 2. Quad SPI I/O Signals
Signal Name PMC MIO Pin MIO-at-a-Glance Table Device Interface Options
Single Dual-Stacked Dual-Parallel
Lower Only Upper Only Lower for both devices Upper for both devices 8-bit data
A B D E E
Lower Interface
QSPI0_CLK 0 0 CLK ~ CLK ~ CLK
QSPI0_CS_b 5 5 CS_b ~ CS_b CS_b CS_b
QSPI0_IO[0] 4 4 IO[0] ~ IO[0] ~ IO[0]
QSPI0_IO[1] 1 1 IO[1] ~ IO[1] ~ IO[1]
QSPI0_IO[2] 2 2 IO[2] ~ IO[2] ~ IO[2]
QSPI0_IO[3] 3 3 IO[3] ~ IO[3] ~ IO[3]
Upper Interface
QSPI1_CLK 12 12 ~ CLK ~ CLK CLK
QSPI1_CS_b 7 7 ~ CS_b CS_b CS_b CS_b
QSPI1_IO[0] 8 8 ~ IO[0] ~ IO[0] IO[4]
QSPI1_IO[1] 9 9 ~ IO[1] ~ IO[1] IO[5]
QSPI1_IO[2] 10 10 ~ IO[2] ~ IO[2] IO[6]
QSPI1_IO[3] 11 11 ~ IO[3] ~ IO[3] IO[7]
Loopback Clock Output
QSPI_LPBK_CLK 6 6 For clock frequencies >37.5 MHz