MIO-at-a-Glance Tables

Versal ACAP Technical Reference Manual (AM011)

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1.5 English

MIO Device Pins

There are 78 sets of signals to control the MIO pins.

  • 52 signals in the PMC MIO (banks 500 and 501)
  • 26 signals in the LPD MIO (bank 502)

Signal Route Control

Many of the IOP controller and other signals are routed to the EMIO by default if they are not specifically routed to MIO pins. The routing for each MIO pin is controlled by a single register, MIO_PIN_xx.

  • Register module with 52 control registers for 52 PMC MIO pins: PMC_IOP_SLCR
  • Register module with 26 control registers for 26 LPD MIO pins: LPD_IOP_SLCR
Note: The MIO signals for the LPD-based controllers can be routed to either the LPD or PMC MIO banks. The selection is done using the LPD_MIO_Sel register. The MIO interface pins for the PMC-based controllers can only be routed through PMC MIO pins.

PL EMIO Signal Route

Some interfaces and signals also go to the PL, and for most interfaces, these are listed in the MIO-EMIO Interface Routing Options section.

MIO Pin Assignments By Banks

The MIO pin assignments are shown in the following tables with links to the chapter sections that list the I/O interface signals.

Note: The pins that can connect to a primary boot device are shaded in the following tables. See Boot Modes section for exact pin usages.
  • Bank 500 includes QSPI, OSPI, and eMMC1 boot interfaces
  • Bank 501 includes SD0 and SD1 boot interfaces
Note: The SelectMAP interface has a programmable width that might include one or more PMC MIO banks.
  • 8-bit interface is on the PMC MIO bank 500
  • 16-bit and 32-bit interfaces require both PMC banks 500 and bank 501