Master Receive

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English
Table 1. I2C Master Receive
Task Register Register Field Bits Operation
Set repeated start if data is more than FIFO depth.
Set hold bit Control, 0x00 HOLD 4 1
Setup master for receiver role (see Setup Master).
Program transfer address Address, 0x08 ADD 9:00 Write address
Setup transfer size Transfer_Size, 0x14 Transfer_Size 7:00 Required transfer size
Enable interrupts IER, 0x24 ARB_LOST, RX_OVF, NACK, COMP 9, 5, 2, and 1
0 227h