Master Receive Polled

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

Table 1. I2C Master Receive Polled
Task	Register	Register Field	Bits	Operation
Set repeated start if data is more than FIFO depth.
Set hold bit	Control, `0x00`	HOLD	4	1
Setup master for receiver role (see Setup Master).
Read interrupt status register	ISR, `0x10`	All	9:0	Read operation
Write back interrupt status register	ISR, `0x10`	All	9:0	Clears bits detected as set
Transfer address	Address, `0x08`	ADD	9:0	Address
Program transfer size	Transfer_Size, `0x14`	Transfer_Size	7:0	Required transfer size
Read interrupt status register	ISR, `0x10`	All	9:0	Read operation
Start Loop 1: perform the following steps as long as receiving bytes and no errors reported from hardware.
Read status register	Status, `0x04`	All	8:0	Read operation
Start Loop 2: perform the following steps as long as RXDV bit is non zero in SR.
Clear repeat start if receive byte count is less than 14	Control, `0x00`	HOLD	4	0
Receive byte	Data, `0x0C`	DATA	7:0	Read operation
Read status register	Status, `0x04`	All	8:0	Read operation
End Loop 2
If receive byte count is >0 and bytes still need to be received.
Read interrupt status register	ISR, `0x10`	All	9:0	Read operation
Write back interrupt status register	ISR, `0x10`	All	9:0	Clears bits detected as set
If receive byte count > maximum transfer size, then program transfer size	Transfer_Size, `0x14`	Transfer_Size	7:0	Maximum transfer size
Else program with required transfer size	Transfer_Size, `0x14`	Transfer_Size	7:0	Required transfer size
Read interrupt status register	ISR, `0x10`	All	9:0	Read operation
End Loop 1
Clear hold bit if not repeated start operation	Control, `0x00`	HOLD	4	0
If any error reported by hardware transfer failed else transfer success.