Master Send Polled

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English
Table 1. I2C Master Send Polled
Task Register Register Field Bits Operation
Set repeated start if data is more than FIFO depth.
Set hold bit Control, 0x00 HOLD 4 1
Setup master for transmitter role (see Setup Master).
Read interrupt status register ISR, 0x10 All 9:0 Read operation
Write back interrupt status register ISR, 0x10 All 9:0 Clear bits detected as set
Transmit first FIFO full of data (see Transmit FIFO Fill).
Program transfer address Address, 0x08 ADD 9:0 Address
Read interrupt status register ISR, 0x10 All 9:0 Read operation
Perform the following steps as long as no errors are reported by hardware from the status register read and total bytes are sent.
Read status register Status, 0x04 All 8:0 Read operation
Read interrupt status register ISR, 0x10 All 9:0 Read operation
Transmit first FIFO full of data (see Transmit FIFO Fill).
Check for transfer completion
Read interrupt status register ISR, 0x10 All 9:0 Read operation
If any error reported by hardware transfer failed.
Clear hold bit if not repeated start operation Control, 0x00 HOLD 4 0