Memory Access Modes

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

There are several flash memory access modes. Only one mode is available at a time.

  • STIG/PIO software triggered instruction generator and programmed I/O
  • Direct mode read/write via AXI slave interface
  • Software non-DMA indirect read/write via AXI slave interface
  • DMA indirect read via AXI master interface

Flash Memory Access Modes Table

Each operating mode uses the system interfaces differently as summarized in the following table. The methods to access the OSPI controls and data differ depending on the operating mode. The features that apply for each mode are identified in the following table.

Table 1. OSPI Flash Memory Access Modes
Entity STIG Direct Mode Indirect Mode
Non-DMA With DMA
Interfaces
AXI system slave ~ Data Data ~
AXI system master ~ ~ ~ Data
APB programming Control and data Control Control Control
Internal DMA peripheral ~ ~ Data  
Hardware Features
Address remap ~ Yes ~ ~
Data write protection ~ Yes ~ ~
DMA ~ ~ ~ Yes
Memory access; flash memory accesses RW RW RW R
Data transfer size per command Up to 8 bytes, or "read memory" up to 128 bytes

Reads up to device size
Writes based on device command

The programmed I/O must not be attempted when there is DMA activity.

STIG, Programmed I/O

Software can trigger individual flash instructions using register reads and writes.

Direct Mode

Direct mode allows software to read and write the memory in the OSPI device using regular read and write transactions on the interconnect. This linear addressing feature is mapped to the address space from 0xC000_0000 to 0xDFFF_FFFF. When the flash memory interface runs in DDR mode, software must always align to an even address and request an even number of bytes. The direct access controller (DAC) receives transaction requests and issues flash memory commands to read and write data.

Direct mode should not be used by a PMC DMA controller when the memory requests are routed through the FPD cache coherent interconnect (CCI). This DMA traffic goes through the LPD main switch on its way to the CCI. This path is shared with the gigabit Ethernet MAC (GEM) controller in the LPD and can cause the GEM to be starved of data. This situation is described in the OSPI Direct Access by PMC DMA via CCI section.

Non-DMA Indirect

The controller can be programmed to read or write a block of data using register read/write operations. For reads, the controller prefetches data in preparation for the software read. For writes, it buffers data for the flash memory.

DMA Indirect

The DMA unit operations are performed by SRC DMA interfaces to the controller's DMA flash interface to read the flash memory via the controller's buffer and the DST DMA to write data to the system memory via the AXI master interface on the PMC IOP switch. The DMA peripheral interface decodes requests from the SRC DMA to read flash memory data.