Memory Coherency

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The reads and writes can be routed to the cache coherent interconnect (CCI) in the FPD for memory coherency with the APU L2 cache. In descriptor mode, the memory coherency parameters for the DMA transfer are sourced from the descriptor table in memory. In the simple register DMA mode, the memory coherency parameters are sourced from APB registers.

  • Register DMA
  • Descriptor table, scatter-gather, SG DMA

The DMA coherent transaction routing to the CCI is controlled by the LPD_INT_CSR.ROUTE_DMA register.

Register DMA

The memory coherency is controlled by the PS_DMA register.

SG DMA

Software programs the SRC and DST descriptors. Software programs registers to point to the start of these descriptors in memory, and enables the channel. Upon receiving a channel enable, the DMA channel fetches SRC and DST descriptors from memory and uses these parameters to perform the actual data transfer. It is the responsibility of the software to program descriptors before enabling a channel.