Memory Map Diagram

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The local memory maps for dual processor and lock-step are shown in the following figure.

Figure 1. RPU CPUs TCM Address Map

Local Address Space at 0xF900_0000

The RPU Arm GIC PL390 interrupt controller occupies 12 KB of local address space starting at 0xF900_0000. This range is only accessible to the RPU via the private low-latency peripheral port (LLPP) interface. For register descriptions, see the RPU_GIC_PL390 register module.

Exception Vectors

The RPU exception vectors can be configured to be HIVEC (0xFFFF_0000) or LOVEC (0x0000_0000). Because the OCM is mapped at HIVEC, and for the RPU to be able to execute interrupt handlers directly from TCMs, the TCMs must be mapped starting at address 0x0000_0000 (=LOVEC). Also, to configure the APU with LOVEC in DRAM, the APU cannot access TCMs at LOVEC. Consequently, TCMs are aliased into a local address map of the RPU for the Cortex-R5F processor to access them starting at address 0x0000_0000.