Whenever a new message (that passes the required filtering) is stored into the RX buffer, the controller updates the respective fill level field of the RxBuff_Status register and sets the APB_MISC_ISR [RXOK] bit.
- As per the requirement, program the RxBuff_Watermark register (WMR) to set full water marks and the [RXFP] field (the WMR register can be set/changed only when [CEN] = 0).
- If required, enable [RXOK] and [RX] Overflow interrupt generation.
- The new message availability can be determined by polling the RxBuff_Status register (FSR) or by a watermark full interrupts indication.
- Read a new message (from RX Buffer 0 or RX Buffer 1) starting from its respective read index location (given in the FSR register field).
- After reading the message, write the FSR register by setting the respective [IRI] bit to 1. This enables the core to increment the respective read index field by +1 and updates the corresponding fill level in the FSR register. If the fill level is 0, setting the [IRI] bit has no effect.
- Repeat steps 3 through 5 until all messages are read from both RX Buffer 0 or RX Buffer 1.
- When a message is successfully received, the core writes the timestamp and matched filtered index field of the received message element.
- The controller increments the fill level of its respective RX Buffer in the RxBuff_Status register (FSR) by 1 after every successful receive (without error and message passes filtering scheme).
- The fill level is also updated by the core after the host writes the [Bx_IRI] bit of the respective RX buffer in the FSR register.