All messages written in the TX buffer should follow the required message format for ID, DLC, and DW fields described earlier. Each [RRnn] bit in the TxBuff_Ready_Req register corresponds to a message element in the TX buffer.
- Poll the TxBuff_Ready_Req register to check current pending transmission requests.
- If all of the register bits are set, a new transmission
request can be added only if:
- One or more buffer transmission requests are canceled, or
- One or more buffer transmission completes
- If one or more bits of the
register are unset/clear,
a new transmission request can be added as follows:
- Prepare one or more message elements in the TX buffers (by writing valid ID, DLC, and DW fields of each message element of the respective TX buffer). If event logging is required for this message element, set the [EFC] bit in one of the TxBuff_DLC_Msg_n registers.
- Enable interrupt generation as required.
- Set corresponding TxBuff_Ready_Req register bits to enable buffer ready requests. The host can enable many transmission requests in one register write.
- Wait for interrupt (if enabled) or poll the TxBuff_Ready_Req register to gather the request status.
- The controller clears the TxBuff_Ready_Req register bit when a respective buffer request is completed (either due to transmission, cancellation, or DAR mode transmission).
- The host can read the TX event buffer to determine the message timestamps and the order of transmissions.
- The controller determines the next highest priority buffer to be transmitted. If two buffers have the same ID, the buffer with the lower index is selected.
- If enabled, copies the ID and DLC fields to the TX event buffer and adds a message timestamp and event type.
- Clears the respective bit in the TxBuff_Ready_Req register when the transmission request is served (either by successful transmission on the CAN bus, cancellation, or DAR-based transmission).
- If enabled through the TxBuff_Ready_Req_Intr_En (IETRS) or APB_MISC_IER (IER) registers, then the APB_MISC_ISR [TXRRS] bit is set = 1 and an interrupt is generated.
TX events status may be useful for software to determine the order of TX buffers and get the transmission timestamp for buffers. This is provided through a separate pipe (TX Event FIFO) so it is de-linked with the individual buffer transmission in the TxBuff_Ready_Req . This separate FIFO should allow software to do this post-processing in batches; asynchronously with respect to individual buffer transmission.