Miscellaneous Configuration, Control, and User Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The USB miscellaneous configuration, control, and user registers are summarized in the following table.

Table 1. USB 2.0 Miscellaneous Configuration, Control, and User Registers
Register Name Offset Address Access Type Description


0x0_C100
0x0_C104

RW Bus configuration

0x0_C110

RW Common control
0x0_C118 R Status

0x0_C11C
0x0_C19C

RW User controls
0x0_C120 Read only ID register
0x0_C124 Mixed General purpose I/O
0x0_C128 Read/Write User ID
0x0_C12C Read/Write Global user control

0x0_C130
0x0_C134

R Bus address error

to

0x0_C140 to
0x0_C15C

R Implementation parameters
0x0_C160 RW, R Queue/FIFO space available
ULPI PHY
0x0_C200 Mixed ULPI PHY configuration
0x0_C280 RW, R ULPI PHY vendor control
RX/TX FIFO Depths



0x0_C300
0x0_C304
0x0_C308

RW RXFIFO 0, 1, 2 depths



0x0_C380
0x0_C384
0x0_C388

RW TXFIFO 0, 1, 2 depths
Event



0x0_C400
0x0_C410
0x0_C420
0x0_C430

RW  




0x0_C404
0x0_C414
0x0_C424
0x0_C434

RW  




0x0_C408
0x0_C418
0x0_C428
0x0_C438

RW  




0x0_C40C
0x0_C41C
0x0_C42C
0x0_C43C

RW  
Host Controls
0x0_C600 R Implementation parameters
0x0_C610 RW Device TXFIFO DMA priority
0x0_C618 RW Host TXFIFO DMA priority
0x0_C61C RW Host RXFIFO DMA priority
0x0_C624 RW Host FIFO DMA high-low priority ratio
0x0_C630 RW Frame length adjustment