The programmable logic includes integrated PLLs, an embedded network of clock routes, and PL clock connections to other parts of the device via the port interface signals.
The MMCM and DPLL clocks are described in the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).
The mixed-mode clock manager (MMCM) generates multiple clocks with defined phases and frequency relationships for a wide range of frequencies, as well as jitter filters for deskew, external, and internal clocks.
The clock input connectivity allows multiple resources to provide the reference clock to the MMCM. There are seven output counters (dividers). MMCMs have 32 step phase interpolators that feed the input of the output and feedback counters, which provides infinite fine phase shift capability in either direction and can be used in dynamic phase shift mode.
The DPLL is a simpler MMCM version of the PLL located in the clocking column next to the HDIO and GT clocking column. Additional DPLLs are co-located in the same tile with MMCMs. DPLLs serve as a digital version of the MMCM for frequency synthesizers for a wide range of frequencies, and as jitter filters for external, internal, or deskew clocks. The functionality and capability of a DPLL are similar to that of MMCM and XPLL.
The XPIO banks include two XPLLs per bank. These have similar features to the MMCM and DPLL clocks. The XPIO banks are programmed by the AMD Vivado™ design tools.