Mode Table

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The control and status bits for the controller modes are listed in the following table. These relate to the Mode Transition figure.

Table 1. CAN Controller Modes
Controller Mode System Reset 1 Software Reset Register (SRR) Mode Select Register, MSR Status Register, SR
Reset [bits] Control [bits] 4 Status [bits]
SRS CEN LBACK SLEEP SNOOP CONFIG NORM SNOOP SLEEP LBACK BSFR PEE
Reset 1 x x x x x 1 0 0 0 0 0 0
0 1
Configuration 0 0
Normal 5 1 0 0 0 0 1
Snoop 5 0 0 1 1 1
Sleep 0 1 0 0 0 1
Loop back 1 0 0 0 0 0 1
BSFR 2 0 x 0 x 0 0 0 1
PEE 3 0 x x x x 0 0 0 1
  1. A hard system reset can be generated by the LPD reset controller using the CRL.RST_CANx [RESET] or one of multiple system-level resets.
  2. The transition to bus-off state depends on the transmit error count value as per standard specification. The recovery from bus-off state depends on the MSR [SBR] and [ABR] settings as per respective bit behavior descriptions. Bus-off recovery can be tracked through status bit [BSFR_CONFIG] bit and the ECR [REC] field. Entry and exit from bus-off state can generate an interrupt.
  3. The transition to protocol exception event state (PEE) depends on the MSR [DPEE] bit.The controller enters and exits the PEE state as per ISO standard specification and this is reflected by the status bit SR [PEE_CONFIG. The entry into the PEE state can generate an interrupt.
  4. An "x" indicates "don't care" for control bits and has no meaning for status bits.
  5. The sample point range should be 50%-80% of bit time for reliable operation.