Monitored Clocks

Versal ACAP Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2022-12-16

Revision

1.5 English

A monitored clock is selected by the CRP.CHKR0_CTRL [MONCLK_SEL] bit field. The ClkMon monitored clocks are listed in the following table.

Table 1. ClkMon Monitored Clocks
[MONCLK_SEL]	Clock Source	Notes
LPD Clocks
`0000`	RPU_REF_CLK
`0001`	LPD_TOPSW_CLK
`0010`	LPD_LSBUS_CLK
`0011`	LPD_SWDT_CORE_CLK	After ref clock source multiplexer
`0100`	LPD_DMA_CORE_CLK	After ref clock source multiplexer
`0101`	PSM_REF_CLK
FPD Clocks
`0110`	APU0_CORE_CLK	At the core (divided by 4)
`0111`	APU1_CORE_CLK	At the core (divided by 4)
`1000`	FPD_TOPSW_CLK
`1001`	FPD_LSBUS_CLK
`1010`	FPD_SWDT_CORE_CLK	After ref clock source multiplexer
PMC Clocks
`1011`	PMC_IRO_CLK
`1100`	PMC_LSBUS_CLK
`1101`	NOC_REF_CLK	NoC interconnect (divided by 4)
`1110`	NPI_REF_CLK
`1111`	REF_CLK pin