The physical layout of all designs is dominated by the NoC interconnect and the programmable logic (PL) with the PMC and PS located together in a corner of the device die. The NoC structure forms a grid in the PL with gigabit I/O transceivers placed along the edges of the perimeter. The entire PMC and PS subsystems are located together in a corner of the device. The DDR memory controllers are located along the bottom edge of the device with the XPIO banks. The AI Engine array, when present, is grouped together along an edge of the device with access to the NoC and the PL.
Not all features are included on a given device. For a complete list of features on a per-device basis, see the Versal Architecture and Product Data Sheet: Overview (DS950).