Monolithic Physical Layout Example

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The physical layout of all designs is dominated by the NoC interconnect and the programmable logic (PL) with the PMC and PS located together in a corner of the device die. The NoC structure forms a grid in the PL with gigabit I/O transceivers placed along the edges of the perimeter. The entire PMC and PS subsystems are located together in a corner of the device. The DDR memory controllers are located along the bottom edge of the device with the XPIO banks. The AI Engine array, when present, is grouped together along an edge of the device with access to the NoC and the PL.

Important: The following figure is an example representation. Some layouts are similar while others can be significantly different in size and features. The following figure does not reflect a specific device. The number of I/O cells and NoC structures varies by device, and sometimes the die is mirrored.

Not all features are included on a given device. For a complete list of features on a per-device basis, see the Versal Architecture and Product Data Sheet: Overview (DS950).

Figure 1. Monolithic Device Physical Layout