Monolithic SoC Die Layout Concept

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

Monolithic devices are the most common. A single silicon die is attached to the package substrate.

The physical layout of all SoC die is typically dominated by the NoC interconnect and the programmable logic (PL) with the PMC and PS located together in a lower corner of the silicon die. The NoC structure forms a grid in the PL. The DDR controllers are located along the bottom side of the die and the integrated hardware options can be located along the left, top, and right sides with gigabit I/O transceivers placed along the outer edge of the of these sides. The AI Engine array, when present, is located along an edge of the device with access to the NoC and the PL.

Not all features are included in a given device. For a complete list of features on a per-device basis, see the Versal Architecture and Product Data Sheet: Overview (DS950).

Note: The following figure is an conceptual representation. Some layouts are similar while others can be significantly different in size and features. The following figure does not reflect a specific device. The number of I/O cells and NoC structures varies by device, and sometimes the die is mirrored.
Figure 1. Monolithic SoC Die Layout Concept