NPI Programming Interface

Versal ACAP Technical Reference Manual (AM011)

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1.5 English

The NoC peripheral interconnect (NPI) provides software with a programming interface path to configure hardware in the SoC domain. The NPI host controller has a large memory space in the PMC to accommodate the register modules for the DDR memory controllers, the optional integrated hardware and peripherals, the I/O, and other hardware. Access to the NPI host controller is managed by the XPPU_NPI_XPPU protection unit. During boot, the NPI is configured when the PMC PLM sends the programmable device image (PDI) NPI partition information to the NPI host controller.

The NPI bus structure is in the SoC power domain and operates completely independent of the NoC interconnect.


The NPI features include:

  • Read/write pathway to the programming control and status registers (PCSRs).
  • Burst read/write transactions.
  • Ordered reads and writes.
  • Early write-response with interrupt error signaling is supported by the PLM firmware in the PPU. The PLM performs writes using EWR at times when there are no other transactions occurring.

System Interrupts

If an NPI register module detects an access decode error, or generates a system interrupt, it is signaled back to the NPI host controller. The system interrupts are routed to several destinations as listed in the System Interrupt Controllers section.