The DMA controller registers are listed in the following table. The base
address for these registers is 0xF101_0000.
| Register Name | Address Offset | Access Type | Description |
|---|---|---|---|
|
|
RW |
Destination DMA address to system memory, 32 LSBs |
|
| DMA_DST_SIZE |
0x1804
|
RW | Destination DMA write payload size |
| DMA_DST_STS |
0x1808
|
R, WTC | Destination DMA status |
|
|
RW | Destination DMA control reg 1 and 2 | |
|
|
WTC |
Destination DMA write interrupt status, enable, disable, and mask |