OSPI DST DMA Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The DMA controller registers are listed in the following table. The base address for these registers is 0xF101_0000.

Table 1. OSPI SRC DMA Register Overview
Register Name Address Offset Access Type Description


            DMA_DST_ADDR_L
        


            DMA_DST_ADDR_H
        

0x1800
0x1828

RW

Destination DMA address to system memory, 32 LSBs
Destination DMA address to system memory, 17 LSBs

DMA_DST_SIZE 0x1804 RW Destination DMA write payload size
DMA_DST_STS 0x1808 R, WTC Destination DMA status


            DMA_DST_CTRL1
        


            DMA_DST_CTRL2
        

0x180C
0x1824

RW Destination DMA control reg 1 and 2


            DMA_DST_ISR
        


            DMA_DST_IER
        


            DMA_DST_IDR
        


            DMA_DST_IMR
        

0x1814
0x1818
0x181C
0x1820

WTC
W
W
R

Destination DMA write interrupt status, enable, disable, and mask