The DMA controller registers are listed in the following table. The base
address for these registers is 0xF101_0000.
| Register Name | Address Offset | Access Type | Description |
|---|---|---|---|
| DMA_SRC_ADDR |
0x1000
|
RW | Source DMA read address |
| DMA_SRC_Status |
0x1008
|
R, WTC | Source DMA read status |
|
|
RW | Source DMA read control Reg 1 and 2 | |
|
|
WTC |
Source DMA read interrupt status, enable, disable, and mask |