OSPI SRC DMA Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The DMA controller registers are listed in the following table. The base address for these registers is 0xF101_0000.

Table 1. SRC DMA Register Overview
Register Name Address Offset Access Type Description
DMA_SRC_ADDR 0x1000 RW Source DMA read address
DMA_SRC_Status 0x1008 R, WTC Source DMA read status


            DMA_SRC_CTRL1
        


            DMA_SRC_CTRL2
        

0x100C
0x1024

RW Source DMA read control Reg 1 and 2


            DMA_SRC_ISR
        


            DMA_SRC_IER
        


            DMA_SRC_IDR
        


            DMA_SRC_IMR
        

0x1014
0x1018
0x101C
0x1020

WTC
W
W
R

Source DMA read interrupt status, enable, disable, and mask