The octal SPI (OSPI) boot mode has an SPI compatible serial bus interface with extended octal commands. The OSPI boot mode supports an 8-bit data bus width and single transfer rate (STR) during the RCU BootROM execution. The BootROM runs at an OSPI device clock frequency between 11 MHz and 24.5 MHz dependent on the REF_CLK setting.
After the BootROM execution, the PLM can support the double data rate (DDR) with strobe for higher performance. For additional information on the OSPI controller, see Octal SPI Controller. For details on OSPI flash device support, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).
The following table lists the STR OSPI commands supported by the RCU BootROM.
| Boot Mode | Data Width | Read Command | Command Code | Dummy Cycles |
|---|---|---|---|---|
| OSPI | 1 | Read |
03h
|
- |
| OSPI | 1 | 4-byte read |
13h
|
- |
| OSPI | 8 | 4-byte octal output fast read |
7Ch
|
8 |
In OSPI boot mode, the device initiates the boot sequence with the
default 4-byte address octal output fast read command code 7Ch and the BootROM searches for a valid boot header. If a valid boot
header is not found, the Versal ACAP attempts to
load the image using the 4-byte alternate addressing read command code 13h. If a valid boot header is still not detected, the
basic read command 03h is tried. If the boot attempt
is unsuccessful after the third command, the BootROM increments the MultiBoot register
(
PMC_MULTI_BOOT
) read
address offset by 32 KB and tries the OSPI command sequence again to locate a valid boot
header. If the OSPI boot mode search limit is reached without a successful boot, the RCU
goes into lockdown and the ERROR_OUT pin is set.
The image search limit for each boot mode is listed in Table 3.