The BootROM sets configuration registers that apply to each boot mode. For octal SPI boot mode, the BootROM sets the registers to the initial values shown in the following table.
Register Name | Base Address | Register Value | Description |
---|---|---|---|
OSPI_REF_CTRL | 0xF126_0120 |
0x0100_0B00
|
Select PPLL divided by 11 (DIVISOR), clock enabled |
MIO_Bank0_Schmitt_En | 0xF106_010C |
0x0000_17BF
|
Enable Schmitt on OSPI MIO pins |
MIO_Bank0_Tristate | 0xF106_0200 |
0x03FF_E840
|
Disable 3-state override on OSPI MIO pins |
RST_OSPI | 0xF126_0304 |
0x0000_0000
|
OSPI RST not asserted |
OSPI_AXI_Sel | 0xF106_0504 |
0x0000_0001
|
OSPI selected |
PMCPLL_CTRL | 0xF126_0040 |
0x0002_4800
|
PMC PLL (PPLL) setup uses reset defaults ( REF_CLK multiplied by 72 (FBDIV) and divided by 4 (CLKOUTDIV)) |