Output Buffer Control Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The buffer output control include output enable and drive strength.

Output Enable

The output enable for each multiplexed I/O buffer is normally controlled by the peripheral controller. There are tristate override registers that can be used to disable an entire bank of signals, if needed.

When the tristate override control bit equals 1, the output on the I/O buffer is disabled and the pin will float according to the weak pull-up or pull-down settings.

Output Drive Strength

The output drive strength is controlled by two bits per output using a bit from a drive 0 register and a bit from a drive 1 register to select 2, 4, 8, and 12 mA drive strength for each individual MIO pin.

MIO Output Buffer Control Registers

The MIO output controls are summarized in the following table.

Table 1. MIO Output Buffer Control Registers
Feature PMC_IOP_SLCR Registers LPD_IOP_SLCR Registers Description
PMC MIO Bank 0 PMC MIO Bank 1 PS LPD MIO Bank 2
Pins 0 to 25 Pins 26 to 51 Pins 0 to 25

Drive strength


            MIO_Bank0_Drv0_Sel
        


            MIO_Bank0_Drv1_Sel
        


            MIO_Bank1_Drv0_Sel
        


            MIO_Bank1_Drv1_Sel
        


            MIO_Bank2_Drv0_Sel
        


            MIO_Bank2_Drv1_Sel
        

drv1 | drv0:
00: 2 mA
01: 4 mA
10: 8 mA
11: 12 mA

Slew MIO_Bank0_Slew_Sel MIO_Bank1_Slew_Sel MIO_Bank2_Slew_Sel

0: Slow-slew
1: Fast-slew

Tristate override MIO_Bank0_Tristate MIO_Bank1_Tristate MIO_Bank2_Tristate

0: Output enable is controlled by the peripheral
1: Output disabled