Over Fetch

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The DMA supports an AXI bus width of 128/64 bits. In the case where the source descriptor payload ends at a non-128/64 bit aligned boundary, the DMA channel fetches the last beat as the full-128/64 bit wide bus. This is considered an over fetch. The over fetch option can be disabled. If an over fetch is disabled and the SRC descriptor payload ends on a non-128/64 bit boundary, the DMA fetches any remaining bytes as a single byte AXI read.

The example in the following figure uses a source descriptor size of 8190 bytes (with a start address at 0x0000_0000 and end address at 0x0000_1FFD), a 128-bit wide AXI bus, and a burst length of 16, the DMA can fetch 256 bytes in a single AXI burst. Two scenarios are provided in this section.

Scenario 1: Over Fetch is Disabled

  • 31 AXI read command with burst length of 16 and AXI size of 16 bytes (7936 bytes fetched).
  • One AXI read command with burst length of 15 and AXI size of 16 bytes (240 bytes fetched).
  • To fetch the remaining 14 bytes, the DMA channel issues 14 single-beat AXI read commands with an AXI size of 1 byte.

Scenario 2: Over Fetch is Enabled

  • 32 AXI burst length of 16 and AXI size of 16 bytes (8192 bytes fetched)
Figure 1. Over Fetch Scenarios