Overflow Detection Mode
If the interval bit in the counter control register is not set, the counter
can count up to or down from its full 32-bit value. An interrupt is generated when
the count passes through zero. To increment, when the counter value register reaches
FFFF_FFFFh, it overflows to zero, and then the overflow
interrupt is set and counting up is restarted. To decrement, when the counter value
register reaches zero, the overflow interrupt is set. The counter then overflows to
FFFF_FFFFh and counting down is restarted.