Versal ACAP Technical Reference Manual (AM011)

Document ID
Release Date
1.4 English

Debug Packet Controller

The debug packet controller (DPC) responds to the commands from the debug host.

SoC Debug I/O

The Versal® ACAP includes device-level debug and trace capabilities. The debug hardware features include the following.

  • Four host debugger access points to the DPC.
    • PCIe® Host: high-speed, high-bandwidth debug protocol
    • Aurora host: high-speed, serial debug protocol path to DPC
    • PL interface: high-speed, high-bandwidth streaming
    • JTAG
  • Debug environment for the following.
    • PS RPU and APU processors
    • PMC and PSM processors
    • PL, CPM, and AI Engine
  • Intrusive and non-intrusive debug.
  • Interfacing to ChipScope™ .
  • Daisy-chaining of multiple devices for debug or configuration through a unified cable.