PCIe Endpoint Mode

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The transactions to and from the CPM are summarized in the following table for the PCIe endpoint mode. The direction of the transaction is reflected in the source_destination route name. The PS designation includes everything that is not the CPM (for example, NoC/DDR).

Note: The root names that include an asterisk (*) include restrictions or programming notes.

Table 1. Transactions in PCIe Endpoint Mode
Route Name	Source	Via	Destination	Notes
From CPM To PS
EP_IN 1	CPM_NOC0	CPM_PS switch, and NoC interconnect	DDR memory or PL	Physical address
EP_IN 2	CPM_NOC0	CPM_PS switch, SMMU TBU 3 CCI, FPD, and OCM switch	OCM memory
EP_IN 3	CPM_NOC0	CPM_PS switch, SMMU TBU 3, CCI, and FPD switch	FPD_AXI_PL interface
EP_IN 4	CPM_NOC1	NoC interconnect	DDR memory or PL	Physical address
EP_IN 5	CPM_NOC0	CPM_PS switch	Debug packet controller
From PS To CPM
EP_OUT 1	APU	CCI, PS_CPM switch	CPM interconnect
EP_OUT 2	PL	NoC interconnect	CPM interconnect
EP_OUT 3	PL_AXI_FPD interface	SMMU TBU 5, CCI, FPD switch, and PS_CPM switch	CPM interconnect
EP_OUT 4	PL_AXILITE_FPD	SMMU TBU 2 CCI, and PS_CPM switch	CPM interconnect
EP_OUT 5	Debug packet controller	PS_CPM switch	CPM interconnect