PCIe Resets on MIO Pins

Versal ACAP Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2022-12-16
Revision
1.5 English

The following table includes the PCIe reset signals routed to the MIO pins. This is a software-defined input signal using a GPIO channel in the PMC GPIO controller.

Table 1. PCIe Controller Reset Input Signals
MIO
Signal Name I/O PMC MUX Pin options LPD MUX Pin MIO-at-a-Glance Table
A B
PCIe_RESET1_b Input 24 38 18 0
PCIe_RESET2_b Input 25 39 19 1