PCIe Root Complex Mode

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The transactions to and from the CPM are summarized in the following table for the PCIe® root complex mode. The direction of the transaction is reflected in the route name: source_destination. The PS designation includes everything that is not the CPM (for example, NoC/DDR).

Note: The root names that include an asterisk (*) include restrictions or programming notes.

Table 1. Transactions in PCIe Root Complex Mode
Route Name	Source	Via	Destination	Notes
Inbound from CPM
RC_IN 1	CPM_NOC0	CPM_PS switch, SMMU/CCI, and NoC interconnect	DDR memory or PL	Set the CCI_CFG_1 [0] bit = 1
RC_IN 2	CPM_NOC0	CPM_PS switch, SMMU/CCI, and FPD to OCM switch	OCM memory
RC_IN 3	CPM_NOC0	CPM_PS switch, SMMU/CCI, and FPD switch	FPD_AXI_PL interface
RC_IN 4	CPM_NOC1	NoC interconnect	DDR memory or PL	Physical address
RC_IN 5	CPM_NOC0	CPM_PS switch	Debug packet controller	Physical address
Outbound To CPM
RC_OUT 1	APU	CCI and PS_CPM switch	CPM interconnect
RC_OUT 2	PL	NoC interconnect	CPM interconnect
RC_OUT 3	PL_AXI_FPD interface	SMMU TBU 5, CCI, and PS_CPM switch	CPM interconnect
RC_OUT 4	PL_AXILITE_FPD	SMMU TBU 2, CCI, and PS_CPM switch	CPM interconnect
RC_OUT 5	Debug packet controller	PS_CPM switch	CPM interconnect