PDI Size Estimation

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The Versal architecture comprises a rich set of adaptable resources. The amount of information required in a PDI to initialize the resources in each Versal ACAP depends on the part number. Because a PDI can also contain user code and data, Xilinx® recommends system architects make an informed estimate of PDI size based on information provided by Xilinx, together with system-specific insights known by the architect. The following table lists the small contributor elements to the PDI size generated by the Vivado/ Vitis™ development system and maximum sizes are provided for estimation purposes.

Table 1. Estimated Maximum Size for PDI Small Contributors to PDI Size
PDI Contributor Maximum Size Maximum Size (Mbits)
Boot header 1 3,968 Bytes <<1
PLM ELF 1 384 KBytes 3
PMC CDO 1 80 KBytes <1
Meta header 1 16 KBytes <1
LPD CDO 1,2 20 KBytes <1
FPD CDO 1,2 20 KBytes <1
PSM ELF 1,2 256 KBytes 2
  1. Size information is based on non-secure, uncompressed images.
  2. LPD CDO, FPD CDO, and PSM ELF element inclusion are dependent on the design.

Additional contributor elements to PDI size are generated by the Vivado/Vitis development system, and when present, are significantly large with sizes depending on the Versal ACAP part number.

  • Programmable logic (PL) configuration frame interface (CFI) information
  • Network on chip (NoC) programming interface (NPI) information
  • AI Engine programming (AI Engine) information

The following table provides size estimation guidance for the larger contributor elements to the PDI.

Table 2. Estimated Maximum Size for PDI Large Contributors to PDI Size
Series Device CFI Maximum Size (Mbits) NPI Maximum Size (Mbits) AIE Maximum Size (Mbits) Total (Mbits)
Versal AI Core VC1352 269 4.5 49.2 322.7
VC1502 507 13.2 76 596.2
VC1702 507 13.2 116.7 636.9
VC1802 715 14.9 115.2 845.1
VC1902 715 14.9 153.6 883.5
VC2602 421 11.1 58.4 490.5
VC2802 421 11.1 116.7 548.8
Versal AI Edge VE2002 39 1.7 3.1 43.8
VE2102 39 1.7 4.6 45.3
VE2202 166 2.8 9.2 178
VE2302 166 2.8 13.1 181.9
VE1752 507 13.2 116.7 636.9
VE2602 421 11.1 58.4 490.5
VE2802 421 11.1 116.7 548.8
Versal HBM VH1522 1516 24.8 - 1540.8
VH1542 1516 24.8 - 1540.8
VH1582 1516 24.8 - 1540.8
VH1742 2172 34 - 2206
VH1782 2172 34 - 2206
Versal Premium VP1002 340 17 - 357
VP1052 522 17 - 539
VP1102 568 20.4 - 588.0
VP1202 842 15.6 - 857.9
VP1402 805 27.7 - 832.5
VP1502 1499 24.8 - 1523.5
VP1552 1516 24.8 - 1540.8
VP1702 2155 34 - 2189.1
VP1802 2812 43.1 - 2854.7
VP2502 1499 25.4 181.2 1705.6
VP2802 2812 43.8 181.2 3037
Versal Prime VM1102 166 2.8 - 168.9
VM1302 277 10.3 - 287.8
VM1402 484 10.3 - 494
VM1502 507 13.2 - 520.1
VM1802 715 14.9 - 729.9
VM2202 421 11.1 - 431.7
VM2302 569 27.7 - 596.3
VM2502 842 15.6 - 857.9
VM2902 805 27.7 - 832.5
  1. Size information is based on non-secure, uncompressed images.

User Code/Data (U-Boot, OS Image, Application, File System)

The remaining image contributors to the PDI size are highly dependent on the system design and cannot be known or provided by Xilinx.

Storing multiple PDI, or multiple images in a PDI, to meet system requirements can multiply the desired storage capacity. Adding boot flow options such as security, compression, or partial reconfiguration can change PDI size.
Note: For PDI that includes PL configuration information, reducing the use of block RAM or UltraRAM initialization (e.g., code/data storage or other ROM-like uses) can decrease the CFI contribution provided in the table estimates in this section.

Due to the many factors that can influence the desired storage capacity, Xilinx recommends system architects model their complete needs using “maximum values” based on information provided in this chapter, coupled with system insight and PDIs generated by the Vivado® /Vitis development system reflecting actual boot flow options and including user code/data.

The desired storage capacity guides the selection of the most appropriate Versal ACAP boot modes. For those boot modes used with a non-volatile memory device, the desired storage capacity also guides the selection process of this additional component.

Boot modes supporting NAND flash technology (i.e., eMMC or SD) provide options for the highest capacity storage, while boot modes supporting NOR flash technology (i.e., QSPI or OSPI) provide options for mid-to-low capacity storage (typically 2 Gbit or lower, with 4 Gbit possible using dual stacked/parallel arrangements). For NOR flash technology, the following table provides guidance on minimum flash component size for storing a single non-secure and uncompressed PDI for a primary boot of a Versal ACAP. The effect of user code/data storage, security, compression, partial reconfiguration, or multiple PDI images is a supplemental consideration.

Table 3. Minimum Flash Component Size for Primary Boot with One Uncompressed PDI
Series Device Minimum Boot Flash Capacity (Mbits)
Versal AI Core VC1352 1024
VC1502 1024
VC1702 1024
VC1802 1024
VC1902 1024
VC2602 512
VC2802 1024
Versal AI Edge VE2002 128
VE2102 128
VE2202 256
VE2302 256
VE1752 1024
VE2602 512
VE2802 1024
VersalHBM VH1522 2048
VH1542 2048
VH1582 2048
VH1742 4096
VH1782 4096
Versal Premium VP1002 512
VP1052 1024
VP1102 1024
VP1202 1024
VP1402 1024
VP1502 2048
VP1552 2048
VP1702 4096
VP1802 4096
VP2502 2048
VP2802 4096
Versal Prime VM1102 256
VM1302 512
VM1402 512
VM1502 1024
VM1802 1024
VM2202 512
VM2302 1024
VM2502 1024
VM2902 1024