PL Flow-Control Interface

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

When the DMA controller accesses a memory in the PL, the flow control interface (FCI) signals are used to provide the data transfer handshake. There are eight sets of FCI signals; a set for each channel. The PS_DMA.CH_FCI register configures the FCI flow control interface.

The PL provides credits to the DMA channel. Each credit is a permission for a single AXI transaction. When the FCI is attached to the SRC (read), there is a permission to generate one AXI data read transaction (write transaction when the FCI is attached to write DST). The following table lists the FCI signals.

Important: The maximum number of credits accepted are 32.
Table 1. Flow Control Interface Signals
Signal Description
PL2DMA_CLK PL clock: signals from/to PL are synchronous to PL2DMA_CLK. The DMA handles all clock domain crossing.
PL2DMA_CVLD Credit valid signal to DMA.
DMA2PL_CACK

Credit acknowledgment from DMA:

  • Credits are accumulated when:
    • PL2DMA_CVLD is High, and
    • DMA2PL_CACK is Low
  • Each FCI can accumulate up to 32 credits.
  • If the FCI is not enabled, then the credits are cleared.
DMA2PL_TVLD Transaction valid.
PL2DMA_TACK Transaction acknowledgment: the DMA channel indicates that one write transaction is done (AXI write command was generated and a BRESP is received) when DMA2PL_TVLD and PL2DMA_TACK are True.

The timing diagram for the flow control interface is shown in the following figure.

Figure 1. Flow Control Interface
Note: The polarity of the CACK signal is reversed from the Zynq UltraScale+ MPSoC device.

Software can configure FCI to flow control either the SRC or DST based on whether the DMA channel is reading from or writing to the PL memory.

  • PL memory reads: program and configured SRC flow control
  • PL memory writes: program and configure DST flow control