PL HDIO Banks

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English
The PL HDIO buffer has the following features:
  • Output control: drive strength and slew rate
  • Settings on a per-bank basis
    • I/O voltage swing:
      • LVCMOS: 3.3V, 2.5V, and 1.8V
      • HSTL: 1.8V
      • SSTL: 1.8V
  • Inputs independently programmed
    • Weak pull-up, weak pull-down, or weak keeper
    • Hysteresis
  • HD IOL logic resources support low-speed interfaces with SDR and DDR logic
  • IODELAY feature with cascadable output delay
  • Coarse data alignment
  • On-die termination
  • Common internal VREF on per bank
  • Receive a differential signal at low-speed
  • Transmit a pseudo differential signal
  • External termination for LVDS and LVPECL inputs

The HD IOL and HD IOB resources in the HDIO banks are described in the Versal ACAP SelectIO Resources Architecture Manual (AM010).

Operating Modes

  • LVCMOS, HSTL, SSTL single-ended signals
  • Transmit single-ended signals with pseudo-differential mode
  • Receive single-ended and differential signals; differential receiver for low-speed clock inputs

System View

The HDIO is arranged in banks of 22 buffers each to connect the PL to the device pins. The PL includes multiple banks of HDIO buffers. The number of HDIO banks varies depending on the device and package size. Examples include the following:

  • Bank 306: PL with 22 pins
  • Bank 406: PL with 22 pins

Programming Model

The I/O characteristics of the HDIO buffers are controlled by the parameters that are configured by the Vivado® design suite wizard.