PL Resets

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

There are four general purpose PL reset signals from the PMC controlled by the CRP RST_PL register:

  • [RESET0]
  • [RESET1]
  • [RESET2]
  • [RESET3]

The register bits are defined as active-High; set the bit = 1 to assert a reset in the PL fabric. The design tools see this reset assertion as an active-Low signal.

These resets are general purpose from the PMC CRP register module to the PL fabric. The uses of these resets are defined by the customer PL design.