PL to PS Interfaces

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The memory protection and coherency features of the PL to PS interfaces are shown in the following table.

Table 1. PL to PS Interfaces
Interface Name Alternate Name APU L2 Cache Coherency Description Register Control
To FPD
PL_ACE_FPD S_ACE_FPD Two-way PL to FPD CCI  
PL_ACP_FPD S_ACP_FPD I/O coherency PL to APU MPCore snoop control unit  
PL_ACELITE_FPD S_AXI_HPC, AFIFM2 I/O coherency PL to FPD AXI Refer to the PL_AFI register module.
PL_AXI_FPD AFIFM0, AFIFM - PL to FPD AXI
PL_ADDR_FPD PLAT - Address translation only from PL to FPD SMMU TBU 6 -
To LPD
PL_AXI_LPD AFIFM4 - PL to LPD AXI Refer to the PL_AFI register module.