PLL Clock Generator Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The PLL clock generator registers are included in four sets of registers: PMC, LPD, FPD, and CPM. The controller names and register sets are listed in the following table.

Table 1. PLL Clock Generator Control Registers
PLL Clock Output Name Power Domain Registers PLL Clock Input Options
Control Register Configuration Register PLL Status Fields
Fields: [RESET], [BYPASS], [FBDIV], [CLKOUTDIV], [PRE_SRC], [POST_SRC] Fields: [RES], [CP], [LFHF], [LOCK_CNT], [LOCK_DLY] Fields: [xPLL_LOCK], [xPLL_STABLE]
PPLL_CLK PMC PMCPLL_CTRL PMCPLL_CFG PLL_STATUS

REF_CLK
PL_PMC_ALT_REF_CLK

NPLL_CLK NOCPLL_CTRL NOCPLL_CFG
RPLL_CLK LPD RPLL_CTRL RPLL_CFG PLL_STATUS

REF_CLK
PL_LPD_ALT_REF_CLK

APLL_CLK FPD APLL_CTRL APLL_CFG APLL_STATUS

REF_CLK
PL_FPD_ALT_REF_CLK

CPLL_CLK PL CPLL_CTRL CPLL_CFG CPLL_STATUS REF_CLK