PMC Block Resets

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The PMC resets for the processors, memory, DMA and other system functional units are summarized in the following table.

Note: All reset register control bits are active-High. A "1" means the reset is asserted.
Table 1. PMC Block Resets
Functional Unit Reset Name Reset Register Control Notes
Processors
RCU RCU_RST Miscellaneous

Internal POR (several sources) and external, dedicated pin  POR_B.
See the Resets Overview section.

PPU PPU_RST Miscellaneous
Peripherals
PMC DMA controllers PMC_DMA_RST


            RST_PDMA
        
[RESET0]

            RST_PDMA
        
[RESET1]

DMAs connect between memory mapped PMC interconnect and the secure stream switch domain.
SBI boot interface module SBI_RST RST_SBI [RESET] The SBI connects the SelectMAP and JTAG boot interfaces to the secure stream switch.
PMC system monitor PMC_SYSMON_RST


            RST_SYSMON
        
[RESET]

Resets the PMC SYSMON controller including register settings and the sequencer configuration.

Note: The eFUSE values are unaffected.
I/O Peripherals
PMC GPIO PMC_GPIO_RST RST_GPIO [RESET] PMC GPIO peripheral controller
PMC I2C PMC_I2C_RST RST_I2C [RESET] PMC I2C peripheral controller
Flash Memory Controllers
QSPI controller QSPI_RST RST_QSPI [RESET]  
OSPI controller OSPI_RST RST_OSPI [RESET]  
SD_eMMC0 controller SD0_RST RST_SDIO0 [RESET]  
SD_eMMC1 controller SD1_RST RST_SDIO1 [RESET]