PMC DMA Features

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The PMC DMA features include the following:

  • Independent datapaths for each source and destination DMA module
    • Source DMA unit fetches data from the memory-mapped space and delivers it to the PMC stream switch interface
    • Destination DMA unit receives data from the stream switch interface and delivers it to a memory-mapped destination
  • Simple DMA register programming, no scatter-gather
  • Each DMA module can accept up to two commands and are stored in the command FIFO
  • AXI4 interfaces
    • 128-bit data width
    • Issue up to nine open transactions
    • Generates secure AXI4 transactions
    • Same SMID for AXI reads and AXI writes
    • Select between INCR and FIXED (keyhole) burst transactions
  • Data FIFOs between AXI4 and AXI-SS are 128 x 128 bits for data and additional bits for sideband signals
    • SRC DMA module only executes an AXI read transaction if there is enough space in the SRC data FIFO to hold the entire data burst size
    • DST DMA module only executes an AXI write transaction if the DST data FIFO has all the data for the burst write by AXI4 interface
  • There are two timeout mechanisms: one for SRC DMA module and one for DST DMA module
  • Interfaces include automatic hardware management of 4 KB boundary crossing for the AXI4 interconnect