PMC DMAs

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The PMC has two 128-bit DMAs. The PMC DMA0 and PMC DMA1 are 2-channel simple DMAs that allow separate control of the read and write channel.

The PMC DMAs primary responsibility is to move data efficiently between the memory-mapped 128-bit AXI interface and the PMC secure stream switch domain. The PMC DMAs move data to and from the cryptographic accelerators (AES, SHA) and SelectMAP through the secure stream switch. The PMC DMAs are not bound to the PMC address space. For example, they can be used to fetch a reconfiguration image from DDR memory. Both PMC DMAs are independent and can be used simultaneously. In the SelectMAP boot mode, the PMC DMA1 is dedicated for the data loading.

The features of the PMC DMAs include:

  • Separate read channel (SRC) and write channel (DST) DMA
  • Read channel fetches data from the PS-side(memory) and delivers it to the PMC stream switch (SS) interface
  • Write channel receives data from the PMC stream switch (SS) interface and delivers it to the PS-side (memory)
  • 128-bit AXI 3.0 interface on the PS-side
  • Deep 128x128-bit data FIFOs for both the SRC and DST datapaths
  • Single thread (single AXI-ID) operation for both read and write channels
  • PMC DMA operates synchronously in the pmc_sec_clk clock domain
  • SRC DMA only issues a read AXI command if there is enough space in the read data FIFO for the entire burst
  • Start address is 32-bit aligned
  • PMC DMA hardware manages alignment between the SS-side and the AXI domain
  • Transfer length is in units of 4-byte (32-bit) words
  • Can accept two commands per channel via a 2-deep command FIFO
  • Timeout mechanisms for both SRC (read) and DST (write) channels
  • Dedicated APB interface for PMC DMA register access